Inductors are a key element of RF-circuits for wireless platforms. Generally, inductors are formed on the surface of the semiconductor chip. However, forming an inductor on the chip surface results in unwanted coupling between the inductor and the circuitry in the die and reduces valuable surface area on the semiconductor chip. Accordingly, it is desirable to replace on-chip inductors with inductors that are integrated into the device packaging. In wafer level chip size packages (WLCSPs), the inductors that are integrated into the package are typically planar inductors. In a planar inductor, the plane of the conductive coil is substantially parallel to the surface of the semiconductor die to which the inductor is connected. Since the device package does not extend beyond the outer perimeter of the semiconductor chip in WLCSPs, planar inductors that are formed in the packaging of WLCSPs have disadvantages that are similar to on-chip inductors. First, in a planar inductor the majority of the magnetic flux lines penetrate into the surface of the semiconductor die. The magnetic flux lines formed by the inductor induce eddy currents that couple back to the inductor and result in an unwanted reduction in the quality factor of the inductor. Additionally, the conductive coil of a planar inductor is located close to the surface of the semiconductor die. The close proximity of the conductive coil to the die surface produces undesirable capacitive coupling between the semiconductor die and the inductor.
One approach to form non-planar inductors has been to use wirebonding techniques to form the conductive coils of the inductor. However, wirebonding coils directly to the surface of the semiconductor die causes significant mechanical stress to the surface of the die. Modern chip technologies use fragile low and ultra low-k dielectrics in the back end of line (BEOL) stack. In many cases the risk of damaging the BEOL-stack by wirebonding is considered too high.